Technical Field
The present disclosure relates to a row decoder, having a reduced area occupation, for a non-volatile memory device, in particular of a flash type, for addressing and biasing rows of the corresponding memory array.
Description of the Related Art
In a known way, and as illustrated schematically in FIG. 1, a non-volatile memory device, designated by 1, for example of a NAND or NOR flash type, generally comprises a memory array 2 made up of a plurality of memory cells 3, arranged in rows (wordlines WL) and columns (bitlines BL).
Each memory cell 3 is constituted by a storage element formed by a floating-gate transistor, with its gate terminal designed to be coupled to a respective wordline WL, a first conduction terminal designed to be coupled to a respective bitline BL, and a second conduction terminal connected to a reference potential (for example, ground GND). In particular, the gate terminals of the memory cells 3 of the same wordlines WL are connected together.
In a way not shown, the memory array 2 is generally arranged in a plurality of sectors, each of which comprises a plurality of memory cells 3. Each sector has a plurality of respective wordlines WL, distinct from those of the other sectors and physically connected to the memory cells 3 present in the same sector.
A column decoder 4 and a row decoder 5 allow selection, on the basis of address signals received at input (generated in a per se known manner and designated as a whole by AS—“Address Signal”, ASr for the rows, and ASc for the columns), of the memory cells 3, and in particular of the corresponding wordlines WL and bitlines BL each time addressed in the various sectors, enabling biasing thereof at appropriate voltage and current values during memory operations.
The column decoder 4 may further be configured to provide internally two paths towards the bitlines BL of the memory array 2 each time selected: a reading path, for defining a conductive path between the selected bitline BL and a sense-amplifier stage 7, designed to compare the current flowing in the addressed memory cell 3 with a reference current in order to determine the datum stored; and a programming path, for creating a conductive path between the selected bitline BL and a driving stage 8, configured to supply the required biasing quantities.
In the specific case of non-volatile memories of a flash type, it is known that memory operations require high values of the biasing voltage applied to the wordlines WL, for example a boosted voltage (high voltage, HV) of 4.5 V, during reading operations. These values of the biasing voltages are generated within the memory device by charge-pump stages, which generate a boosted voltage starting from a supply voltage Vdd with logic value, for example a low voltage (LV) of 1.2 V.
The row decoder 5 thus usually has a configuration with a low-voltage portion (i.e., a portion operating with voltages in the region of the supply voltage Vdd, for example 1.2 V) and a high-voltage portion (i.e., a portion operating in the high-voltage range, i.e., with voltages in the region of the boosted voltage, for example 4.5 V), which is to be coupled to the wordlines WL of the memory array 2 for supplying the required biasing quantities. Level shifters are used for shifting the low-voltage signals (for example, 1.2 V) of the first portion of the row decoder 5 to high-voltage signals (for example, 4.5 V) of the second portion of the row decoder 5.
As illustrated schematically in FIG. 2, in a known embodiment, the row decoder 5 includes an input module 10, which receives the row address signals ASr, digital signals having a certain number of bits, from an input-address bus 11, and appropriately groups together the bits of the same row address signals ASr into subsets, in order to generate low-voltage grouped address signals PASLV.
The row decoder 5 further includes a pre-decoding module 12, which receives the grouped address signals PASLV and combines them logically in an appropriate way, to generate low-voltage pre-decoded address signals PASLV, on a first transport bus 13, which includes a certain number of lines, each of which corresponding to a respective combination of the grouped address signals PASLV.
Through the aforesaid first transport bus 13, the low-voltage pre-decoded address signals PASLV then reach a voltage-booster module 14, which receives at input the low-voltage pre-decoded address signals PASLV and generates high-voltage pre-decoded address signals PASHV on a second transport bus 15, which includes a number of lines corresponding to the number of lines of the first transport bus 13.
The row decoder 5 further includes a decoding module 16, which receives the pre-decoded address signals PASHV and combines them logically in an appropriate way for generating decoded address signals DASHV, which are also high-voltage signals, on an output bus 17, which includes a number of lines corresponding to the number of wordlines WL of the addressed sector of the memory array 2. A driving module 18, which receives the decoded address signals DASHV from the output bus 17 and generates appropriate high-voltage biasing signals S_WL for the respective wordlines WL of the sector of the memory array 2, so as to perform addressing and biasing of the corresponding memory cells 3.
Row-decoder architectures 5 substantially similar to what described above are illustrated for example in:
P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, “Flash Memories”, Kluver Academic Publishers, 1999, Chapter 5.2;
G. Campardo, “Progettazione di memorie non volatili”, Franco Angeli 2002, pp. 199-205, which is incorporated herein by reference, in its entirety.
In greater detail, and with reference to FIG. 3, in a known embodiment of such a row decoder 20, the row address signals ASr (for example, nine-bit digital signals) are received by the input module 10 of the row decoder 5 and grouped appropriately into subsets in order to generate the grouped address signals PASLV, here designated by way of example as: px (referred to in what follows “as first address signals”), lx (referred to in what follows as “second address signals”) and ly (referred to in what follows as “third address signals”).
For instance, considering a row address signal ASr<8:16>, the first address signals px may correspond to the three bits ASr<8:10>, the second address signals lx may correspond to the two bits ASr<11:12>, and the third address signals ly may correspond to the remaining four bits ASr<13:16>.
The input stage 10 further generates, based on the row address signals ASr, fourth address signals ls.
For instance, the fourth address signals ls may indicate the sector of the memory array 2 that is to be selected, the first address signals px may indicate a block (in the example, of eight wordlines WL) to be addressed within the sector, and the second and third address signals lx and ly may indicate the specific wordlines WL to be addressed within the selected block.
The pre-decoding module 12 comprises a plurality of first logic gates 24, of a two-input, one-output NAND type, each of which receives at the inputs a respective first address signal px and a respective fourth address signal ls and supplies at the output a respective first low-voltage pre-decoded address signal, here designated by psx.
In the example described, the first logic gates 24 are eight in number (i.e., in a number equal to the number of combinations that may be obtained starting from the address signals received at the input).
The pre-decoding module 12 further comprises a plurality of second logic gates 25, of a three-input, one-output NAND type, each of which receives at the inputs a respective second address signal lx, a respective third address signal ly, and a respective fourth address signal ls, and supplies at the output a second low-voltage pre-decoded address signal, here designated by sxy.
In the example described, the second logic gates 25 are sixty-four in number (i.e., once again in a number equal to the number of combinations that may be obtained starting from the address signals received at the input).
The first transport bus 13 comprises in this case eight lines for the first low-voltage pre-decoded address signals psx, and sixty-four lines for the second low-voltage pre-decoded address signals sxy, which are received at the input of the booster module 14.
The booster module 14 comprises a plurality of first booster stages 26, each having an input that receives a respective first low-voltage pre-decoded address signal psx and an output that supplies a respective first pre-decoded address signal psxhv, having a high voltage. In the example, the first booster stages 26 are in a number equal to eight.
The booster module 14 further comprises a plurality of second booster stages 27, each having an input that receives a respective second low-voltage pre-decoded address signal sxy and an output that supplies a respective second pre-decoded address signal sxyhv, having a high voltage. In the example, the second booster stages 27 are sixty-four in number.
The decoding module 16 comprises a plurality of buffer stages 28, operating as inverters, each receiving a first pre-decoded address signal psxhv and supplying at an output, on the second transport bus 15, the negated version of the first pre-decoded address signal, designated by psxhvn. For instance, in the embodiment illustrated, a hundred and twenty-eight buffer stages 28 are present (which appropriately enable an increase of the fan-out at output from the first booster stages 26).
The decoding module 16 further comprises a plurality of logic-combination stages 29, each having a first input that receives a respective first negated pre-decoded address signal psxhvn from a respective buffer stage 28, a second input that receives a respective second pre-decoded address signal sxyhv from a respective second booster stage 27, and an output that supplies a respective decoded address signal DASHV.
Each logic-combination stage 29 implements an OR logic operation between the pre-decoded address signals to be combined received at the input: psxhvn and sxyhv.
The decoded address signal DASHV thus has a high value (high voltage) when any one, or both, of the pre-decoded address signals to be combined, psxhvn and sxyhv, have a high value, and a low value (ground, GND) when both of the pre-decoded address signals to be combined, psxhvn and sxyhv, have a low value.
In the embodiment illustrated, the logic-combination stages 29 are five hundred and twelve in number, i.e., equal to the number of wordlines WL to be addressed (and to the total number of combinations between the pre-decoded address signals to be combined psxhvn and sxyhv).
The driving module 18 of the row decoder 5 comprises in this embodiment a plurality of inverters 30, each having an input that receives a respective decoded address signal DASHV and an output that supplies the corresponding biasing signal S_WL for the respective wordlines WL of the memory array 2. The number of inverters 30 is equal to the number of the wordlines WL to be addressed, in the example, five hundred and twelve.
In detail, each inverter 30 comprises a first output transistor 31a, of a NMOS type, having its control terminal that receives the respective decoded address signal DASHV, its drain terminal that is connected to a respective wordline WL and on which the corresponding biasing signal S_WL is present, and its source terminal that receives a reference voltage Vref, which may possibly have a negative value (or be equal to the ground reference GND). A second output transistor 31b, of a PMOS type, has its gate terminal that receives the respective decoded address signal DASHV, its drain terminal that is connected to the respective wordline WL and on which the corresponding biasing signal S_WL is present, and its source terminal that receives a boosted voltage, here designated by Vx, for example equal to the high voltage of 4.5 V.
To a low value of the decoded address signal DASHV corresponds a high output of the inverter 30, with the corresponding biasing signal S_WL equal to the boosted voltage Vx. Instead, to a high value of the decoded address signal DASHV corresponds a low output of the inverter 30, with the corresponding biasing signal S_WL equal to the reference voltage Vref.
A more detailed description is now made, with reference to FIG. 4, of a known circuit embodiment of a logic-combination stage 29 of a standard CMOS type.
The logic-combination stage 29 comprises six MOS transistors, namely a first pair of input transistors, of a NMOS type, connected in parallel, and a second pair of input transistors, of a PMOS type, connected in series, which are designed to jointly implement the operation of OR logic combination of the pre-decoded address signals to be combined psxhvn and sxyhv received at the input, and a pair of output transistors, designed to supply on an output out the decoded address signal DASHV according to the result of the aforesaid OR logic combination.
In particular, in the first pair of input transistors, a first NMOS transistor 32a is connected between a first reference line 33, set at a first reference potential, for example equal to the reference voltage Vref, and an internal node 34, and receives on a respective control terminal a respective first negated pre-decoded address signal psxhvn, and a second NMOS transistor 32b is connected between the first reference line 33 and the internal node 34, and receives on the respective control terminal a respective second pre-decoded address signal sxyhv.
In the second pair of input transistors, a first PMOS transistor 32c and a second PMOS transistor 32d are connected in series between the internal node 34 and a second reference line 35, set at a second reference potential, for example equal to the boosted voltage Vx, and receive on a respective control terminal the second pre-decoded address signal sxyhv and the first negated pre-decoded address signal psxhvn, respectively. In the pair of output transistors, a pull-up PMOS transistor 32e is connected between the second reference line 35 and the output out, and has its control terminal connected to the internal node 34, and a pull-down PMOS transistor 32f is connected between the first reference line 33 and the same output out, and has its control terminal that is also connected to the internal node 34.
It is evident that the logic-combination stage 29 implements the following truth table in the OR logic combination of the pre-decoded address signals to be combined sxyhv and psxhvn:
sxyhvpsxhvnDASHV111101011000
In particular, when at least one of the pre-decoded address signals to be combined sxyhv and psxhvn has a high value, or when both of the pre-decoded address signals to be combined sxyhv and psxhvn have a high value, the internal node 34 is set at the reference potential (given the closed state of one or both of the NMOS transistors 32a, 32b of the first pair). Consequently, the pull-up PMOS transistor 32e is closed, and the output out goes to the high value (boosted voltage Vx).
When, instead, both of the pre-decoded address signals to be combined sxyhv and psxhvn have a low value, the internal node 34 is set at the high value (boosted voltage Vx), given the closed state of both of the PMOS transistors 32c, 32d of the second pair. Consequently, the pull-down PMOS transistor 32f is closed and the output out goes to the low value (reference voltage Vref).
The present Applicant has realized that the row-decoding solution described previously has some limitations, in particular associated to a high occupation of area, which may prove important in applications where size reduction is required (for example, in portable applications).